Digital Front-End Design
RTL development (VHDL/Verilog/SystemVerilog)
Microarchitecture definition , FSM and datapath design
IP integration
Low-power RTL design
Block-level design & Subsystem integration
SoC integration
IP Design and Integration
Protocols like AMBA (AXI/AHB/APB) based designs
UVM verification & Testbench development
Functional coverage
Assertion-based verification (SVA)
Debug, root-cause analysis & Regression management
Formal Verification
FPGA implementation
Hardware validation
Design bring-up
Performance evaluation
Digital Back-End Design
RTL-to-Gate level synthesis
Constraint development
Performance, Area & Power Optimization
Floorplanning
Power planning
Placement
Clock Tree Synthesis (CTS)
Routing
Physical verification
Timing constraint development
Timing analysis
Timing closure
ECO support
Scan insertion
ATPG support
Test coverage analysis
MBIST/LBIST support
Timing signoff
Physical signoff support
Timing signoff
Tape-out readiness
Analog Front-End Design
Amplifiers/Comparators
PMIC
Data converters & ADC/DAC design
Interface circuits & Analog-digital integration
RF and Wireless
Pre-layout simulations
Corner analysis
Monte Carlo analysis
Performance validation
Analog Back-End Design
Standard Cell Layout
Analog Layout / RF Layout / High Speed Layout
Memory Layout
IO Layout
Design Rule Check / Design for Manufacturing
Layout Vs Schematic / Electrical Rule Check
Parasitic Extraction / Reliability Verification
Antenna check/Density check